1. Field of the Invention
The present invention relates to an amplification circuit, and more particularly to an amplification circuit, having a feedback resistor circuit and a power-save circuit, which amplifies analog signals input thereto via an AC coupling capacitor. The present invention also relates to an integrated circuit having the amplification circuit.
2. Description of the Related Art
In recent years, an LSI chip in which analog circuits and digital circuits are formed as a system-on chip to provide many functions and operate at a high speed has been proposed. In such an LSI chip, an amplification circuit in which a feedback circuit and a power-save circuit are arranged is often provided. The amplification circuit efficiently amplifies analog signals input thereto via an AC coupling capacitor. It is desired that such an amplification circuit can operate at a further high speed and a starting time of the amplification circuit can be shortened.
A conventional amplification circuit is formed as shown in FIG. 1. Referring to FIG. 1, an amplification circuit 90 amplifies analog signals input thereto via an AC coupling capacitor 50. The amplification circuit 90 has an amplifying unit 10, a feedback resistor 20 and a power-save circuit 40.
The feedback resistor 20 is provided in a feedback line of the amplifying unit 10 formed of a P-channel transistor 11 and an N-channel transistor 12. An operating threshold level of the amplifying unit 10 depends on a level (e.g., about 1/2 VDD) at which drain currents of the N-channel transistor 12 P-channel transistor 11 are balanced by the feedback resistor 20. In the amplification circuit 90, the larger the resistance value of the feedback resistor 20, the larger the signal amplification factor of the amplifying unit 10. Thus, the feedback resistor 20 is set at a value as large as possible.
The power-save circuit 40 clamps the potential level at an input node Pi1 at zero to decrease the consumed power of the amplification circuit 90. In the power-save circuit 40, the source terminal of an N-channel transistor 41 is grounded. The power-save circuit 40 is provided with a power-save signal PD from an external unit. When the power-save signal PD has a high level, the transistor 41 is in an on state, so that the potential level at the input node Pi1 to which the signal is input is clamped at zero. When the potential level at the input node Pi1 is zero, the P-channel transistor 11 is in the on state and the N-channel transistor is in the off state, so that the output node Po0 has the potential level equal to VDD.
When the amplification circuit is activated, the power save signal PD becomes the low level so that the transistor 41 is turned off. The electric charge is thus supplied from the output node Po0 having the potential level of VDD to the input node Pi1 having the potential level of zero via the feedback resistor 20. The potential level at the input node Pi1 is restored to about 1/2 VDD which is the operating threshold level of the amplifying unit 10. While the electric charge is being supplied to the input node Pi1, the potential level at the output node Po0 is decreased to about 1/2 VDD so as to be balanced with the potential level at the input node Pi1.
When the potential level at the input node Pi1 reaches the operating threshold level of the amplifying unit 10, the amplifying unit 10 starts the amplifying operation. As a result, an analog signal input to the amplifying unit 10 via the AC coupling capacitor 50 is inverted and amplified. The output signal of the amplifying unit 10 is output via the output node Po0.
In the conventional amplification circuit 90 as described above, in order to restore the potential level at the input node Pi1 from the clamped level of zero to the operating threshold level, the electric charge passes through the feedback resistor 20 which is set at a value as large as possible to obtain a large signal amplification factor and a low consumed power. Thus, a long restoring time is needed to restore the potential level at the input node Pi1 to the operation threshold level.